This page describes a circuit which can test the impact of jitter in digital audio systems. A DDS circuit in a FPGA is used to drive a digital output pin with a jittering signal. Measurements are done to find the budget of jitter tolerance. Here a TASCAM TM D1000 digital console is tested. For initial information about the impact of jitter, see this article: jitter in audio systems.

The Test Circuit

The circuit generates a precise sine wave at 24 bits eventually modulated in frequency and amplitude. The jitter is then introduced by noise circuit controlling a dynamic delay buffer operating like described in the digital noise generator article. Thus phase noise is introduced into the signal.

During the test, the phase noise is increased and the output clock from the mixing console is measured. As expected, the input circuitry of the TASCAM Mixing Console is pretty tolerant against noisy jitter at least regarding high frequent jitter rejection. This leads to the fact that below 0,25% jitter, there will be no glitches at all in the final clock system and the mixing console is stable. But when looking at the jitter of the output signal, one can observe that low frequent jitter can hardly be suppressed by the circuit but has an increasing impact.

As shows in the diagram the low frequent jitter more and more influences output signal.

The Impact of Jitter on ADCs

Another idea was to feed the internal ADCs with a precise analog sine wave and directly observe the impact of the incoming clock jitter and compare it with the internal clock. As the diagram shows, a small jitter of 0,1% at 50 Hz causes already a distortion of the sampled sine wave. Without the extra jitter, only the internal clock jitter influences the sound and this is not very much.

Conclusion and Summary

 Jitter in S/PDIF signals cannot totally be eliminated by the input clock circuitry but has an impact on sound quality.