1024 Samples RAM
VHDL Block Design
Signal flow in the PLD
An optimized DDS module is used to
equip the workstation with a precise wave table based sound generation.
Using either DDS-based frequency generation or VA-modeled sine wave
operation, a trigger sine wave is used to control the current phase
of the sound signal.
According to the given frequency setting a
multiple of it is used to generate the address for the SRAM in the
FPGA leading to a precise phase relation of both the triggering
wave and the generated wave thus eg 256, 512 or even 1024 dots per
period can be accessed progressively. Any waveform can be loaded
into the block ram so true wave table synthesis is performed. Phase
jitter is eliminated by oversampling the wave with the FPGA clock
frequency. For a 12 kHz wave, 4096 samples are used to generate
the 4 samples for the 48kHz output using a CIC + FIR filter. Blockram
is accessed my UART.
Real time S/PDIF sampling is planned.
Signals from the PLD
Example Waves on VGA Oscilloscope view
See also Reverb Module.