advanced audio recording

High Precision Audio Resampling-Filter

24 Bit

Block Diagram

A high precision 44,1kHz to 96kHz resampler

Clock Generation

A 63,500 MHz PLL is tuned the analog way by influencing the load capacitor to dynamically adapt to an incoming frequency of 44,1kHz which is achieved by dividing its output by 9 and deriving half of a frequency coming close to a fraction of the dedicated resampling frequency of 14,112 MHz which again is an integer multiple of both 44100Hz and 96000Hz. By comparing the phases of the external and internal clock and switching the load an output frequency is generated with in in phase in the long run. The tuning information is obtained from an analog comparator which takes both the internal and the external 44kHz clock into account and provides information to the shift control circuit which switches a capacitor working as a load for the PLL. The internal resampling frequency MCLK is then generated by a low jitter PLL mitigating these regulation artifacts down to less than 100ps.


The incoming data is handled by an asynchronous FIFO which avoids any false sampling because of incoming jitter. The data is then upsampled to the resampler frequency MCLK and driven into a CIC-filter transforming the data from one domain to the other.

By decimation and post filtering a clean wave with an edge frequency of around 18kHz is derived. This ommits possibly aliasing caused by the CIC-Filter.

The example circuit is running on a Spartan 3E Eval PCB.

VHDL vailable for purchase.

See the former version of the resampler: 44,1kHz to 48kHz

96 kHz
Audio DSP


© 96kHz.org 2006