advanced audio recording

High Precision Resampling-Filter

24 Bit

Block Diagram

A high precision 44,1kHz to 48kHz resampler

Analog Part

A 55 MHz PLL is tuned the analog way to dynamically adapt to an incoming 44,1kHz frequency, by dividing by 39 thus deriving a a frequency which comes close to a fraction of the dedicated resampling frequency of 7,056 MHz which is an integer multiple of both 44100Hz and 48000Hz. The internal resampling frequency MCLK is then generated by a low jitter PLL mitigating the regulation artifacts down to less than 0,1ns.

The tuning information is obtained from an analog comparator which takes both the internal and the external 44kHz clock into account and provides information to the shift control circuit which switches a capacitor working as a load for the PLL.

Digital Part

The incoming data is handled by an asynchronous FIFO which avoids any false sampling because of jitter. The data is then resampled up to the resampler frequency and driven into a CIC-filter transforming the data from one domain to the other.

By decimation and post filtering a clean wave with an edge frequency of around 18kHz is derived.

The example circuit is running on a Spartan 3 Eval PCB.

48 kHz
Audio DSP


© 96kHz.org 2004