This page shows the basics of virtual analog modeling with digital equations and a concept to realize it in an PLD.

a self oscillating circuit

An easy oscillator can be built using two accumulators with a feedback path and scaled factors using the subsequent logic elements:

The adders accumulate the incoming scaled values and thus act as integrators. While the first accumulated value acts as a kind of speed, the second one is the position and the inverted acceleration. The resulting equations for this case are a classical differential equation system and lead to a sine wave - the known solution for mechanical and electrical systems which oscillate. To use this directly in C language it is possible to use the REAL type for the variables when performing the calculation.

For Verilog and e.g. GHDL this has to be treated in a different way:

virtual oscillating circuit in integer

INTEGER calculation is used in this case and precise rounding techniques will have to be applied to get a sufficient accuracy and avoid issues caused by vector cropping:

With this circuit a permanently running oscillator is realized if feedback factors are set properly to get a stable system. The resulting frequency and amplitude are implicitly given and can be indirectly controlled in that way, that the multiplier values are changed. To switch it on or modify the output level, the final multiplier stage is used as a gate. It also compensates the variation of the amplitude with the frequency. The detailed values including a certain offset for both velocity and amplitude will depend on the starting conditions.

from digital to analog

Although the above stage of the oscillator works fine, it is still far way from being analog. Dirt effects will have to be added in order to obtain a more realistic behavior whereby one is most essential: Real circuits will always come with loss effects which at first glance seem to be a problem but are not when having a closer look at this issue: Loss will surprisingly add stability to the circuit and also solve the offset problem.

In the subsequent version of the circuit, noise is added to achieve analog dirt and a noise shaped rounding method to lower coarseness. Also another feedback line is added by looping back the volume level which performs first order damping and BIAS removal.

The noise shaping is required to overcome the rounding issues causes by the limited vactor sizes. Here it is done with a very easy noise generator using a binary counter together with the bit flip method. Better results can be achieved when using counters with non binary lengths and optimized progressing steps. LFSRs are best for this but require more space than just the counter, because processing is required.

The cirtuit has been successfully tested in a set of PALs using GHDL (GenRad's Hardware Description Language) and modern V-HDL in Xilinx XC 3000 devices. Using a clock connection the very last lane (feedback F) the oscillator runs in closed loop method. Maximum delay achieved was less than 10ns per stage -> 100ns for the single loop. Using a 10:1 distance for clocking against synthesis frequency, this makes 1MHz sine waves possible.

However this requires large vector sizes which hardly fit into such a device. So lower clocking with more registers is more appropriate. A 8-bit sine was done as an example with 120kHz this way. 

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