|Advanced Audio Recording|
Frequency Shifting with Sub Sample Delay
For audio and music applications with DDS or jitter compensation, it is often necessary to slightly change the frequency of a clock for some percentages which is mostly a problem in digital domains: When resampling an incoming signal, all periods are multiples of the sampling period which often is too coarse.
This page shows an example for direct frequency tuning by just adding short delays into the signal. Performing this dynamically it is possible to slow down or accelerate a given clock frequency by only a very small percentage the smoothed way.
Sub sample periods can be added this way leading to a very precise frequency shifting.
The example above shows a circuit being appropriate for up to 100 MHz. It is capable to change the frequency in 1/256 steps. By e.g. adding a time step every 100th clock cycle, the resulting frequency was 96,000003 Hz. The shifting was performed this way on Cyclone Altera FPGA and in the first version done at a slower Spartan 2 FPGA. See the Spartan 2 platform. Because the newer FPGAs are much quicker, it requires some chaining of LUTs in order to achieve the desired delay or 0,65ns. The FPGA Editor is used for this.
by simply switching between the delayed clocks in forward or backward direction the resulting frequency is lowered / increased slightly. This can be done in smaller periods than the sample clock. With an intelligent control circuit, vibrato can be added to the sound effectively.
Classical DDS techniques can be enhanced by dynamically shifted clock frequencies leading to a smoothed behavior and low jitter
Read an earlier article about Smoothed Frequency Shifting
|© 2008 J.S.|