Resampling Audio Player Module
g this dynamically it is possible to change a given clock frequency by only a small percentages.
With this circuit is it possible to resample an incoming audio
data stream to a given internal or external 96kHz frequency for
ideal phase synchronisation. This is
essential when adding more than one sources in digial audio domains.
Using the magic 29/59 ratio for the MUL/DIV configuration a nearly
perfect S/PDIF clock of 64 x 96kHz is obtained from any normal 25
MHz clock oscillator. The built in feedback path of the FPGA PLL is
used to synchronize the internal clock effectively.
Using digital up conversion with progressive filtering techniques an equation is
continously generated which represents the current signal behaviour
of the dedicated period. Taking the new time base on the right side
of the resampling unit into account, a new value is calculated by
the interpolating equation.
Resampling thus is performed beyond clock domain boundaries.
The data is stored into a ream to be continously replayed creating a
real time audio sample player.
Read more details about the function of the circuit in the article
about the Resampler Module