g this dynamically it is possible to change a given clock frequency by only a small percentages.

With this circuit is it possible to resample an incoming audio frequency to the given internal or external frequency in the range of 96kHz. This is essential when adding more than one sources in digial audio domains. Using the magic 29/59 ratio for the MUL/DIV configuration a nearly perfect S/PDIF clock of 64 x 96kHz is obtained from any normal 25 MHz clock oscillator. The built in feedback path of the FPGA PLL is used to synchronize the internal clock effectvely.

Using commonn digital up conversion with a special progressive filtering technique an equation is continously generated which represents the current signal behaviour of the dedicated period. Taking the new time base on the right side of the resampling unit into account, a newvalue is calculated from the interpolating equation.

 Resampling is thus performed beyond clock domain boundaries. The resampler can additionally be equipped with input synchronisation FiFos in order to reduce jitter.

Read about the detailled function of the circuit in the article about the Frequency Converter