A ladder filter similar to classical
MOOG-filters is built in VHDL to be integrated into the workstation.
Therefore the analog behaviour is investigated in order to emulate
non ideal effects. This includes noise, non linearity of the transistors,
heating effects, capacitance non linearity, saturation effects
and PCB effects like cross
talk and wire resistance / capacity against GND. Also capacity
of the pins are modelled. The circuit is described using
standard components and C-language like equations, formerly
created to be placed
into the ABM-blocks in pSPICE. They were transformed into a pipeline model
in VHDL for FPGAs.
Read an article about analog modelling: