g this dynamically it is possible to change a given clock frequency by only a small percentages.

With this circuit it is possible to generate any of the desired audio frequencies like 44100Hz, 88200Hz and 176400Hz from any of the given input frequencies like 96000Hz and common 48000Hz. Also the new 192000Hz planned for future audio systems is possible. With two units in parallel it is possible to do this vice versa. Unlike manual adjustment pf the target phase by controller adding delays to the signal, a PLL with explicit clock fedback is use to generate the two different master frequencies 12,8 / 11,3 MHz. Finetuning is performed by frequency transformation circuit though.

Resampling is performed with one ore two resampling units shown below:

Resampler Unit



The resampler is built with an input synchronizer (asynchronous FIFO created from FPGA blockram) a clock domain cross circuit with eventual interpolation and both a cascaded integrated comb filter known as a Hogenauer-filter and an attached steep low cut filter acting at 22500 Hz for 44100-systems or 24000 Hz for 48khz-system respectively to perform anti aliasing filtering. For optimal use the CIC is configured at 3/4 edge frequency leading to a 3dB edge of 16500Hz / 18000Hz meeting the audio range. The total latency of the signal is about 20 ccs w/o the processing of the S/PDIF units.


Read about the detailled function of the circuit in the article of the former version of the Frequency Converter