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PLD SYNTH
48kHz x 16 Bit
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FPGA-Platform
Xilnx
Spartan 3E
An Spartan
3E platform is used to implement a design for my
PLD-Synthesiser.

The circuit is a complete VHDL-implementation of my music
synthesizer wich formerly was built for Xilinx XC4000 PLDs and following.
Because of the greater resources, some additional functions could
be integrated, which already had been used in the C-Version on my chameleon synthesiser.
Circuit Function
The design uses
the DDS method with a given tuning word. This is derived from a
frequency information of the MIDI word and progresses a phase counter.
Together with the vibrato information, this generates a phase value
for to the waveform generators.

The phase counter is directly used as a sawtooth. The
triangle is generated by flipping the bits partially when the
phase counter is greater than 50%. The sine wave can be done in
two ways by
diode clipping or super imposing waves:
As in the first
version the third harmonic is subtracted from the
actual triangle. The phase of that harmonic is generated by
shift-and-add processing like 3 * phase = 2* phase +
phase, so no multiplicatin is required. Additionally a 5th
harmonic is introduced. The final sine wave than is sin
(f) = tria(f) + a * tria (3f) + b * tria (5f). I found 1/8 and
1/24 for a and b.
This produces almoset a good sine-like tone.

The quality
could be furtherly increased if the chip had more resources to
implement more waves. With forthcoming FPGAs
more waves shall be possible. However unlike in the PLD version
we have more options for math processing so diode clipping as
inthe famous 8038 can be applied:

Due to limited space, modulation
via the parameters and the ADSR is also still coarse in
comparison to analog synthesisers.
Read about the former
circuit PLD-Synthesiser
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