A reverb module using delays in VHDL
(c) 2011 Jürgen Schuhmacher
Reverb is generated by processing wall reflections of various sound sources in a virtual room.
Validation of Reverb
See the former website : reverbtest
Delay - Synthesis Unit
Logical representation of the FPGA Design.
FPGA - Design Spartan 6 FPGA
Physical part of the FPGA Design (IO wrapper). Reset Logic is added to control the PLLs.
Plattform: Digital Audio Workstation in VHDL
Verification - Simulation
Digilent Atlys and Terrasic De 115 are used to demonstrate the reverb in VHDL:
FPGA - Hardware Spartan 6
FPGA - Hardware Cyclone 4
Demos
Download a reverb example for Terasic DE2-115 FPGA board: terassicreverbtest.zip
Download an echo delay example for Digilent Atlys FPGA board: atlysaudiotest.zip
Jürgen Schuhmacher - 2012