A reverb module using delays in VHDL

(c) 2010 Jürgen Schuhmacher

 

Reverb is generated by processing wall reflections of various sound sources in a virtual room.

 

Validation of Reverb

Virtual microphones are used to collect the information from various angles.

 

Stereo and Decca Recording

Decca Recording

See more information for DECCA here:

DECCA Sound Source Localization.

 

Delay - Synthesis Unit

Music Delay Unit for Cyclone II FPGA

Logical representation of the FPGA Design.


 

FPGA - Design Spartan 3 FPGA

Physical part of the FPGA Design (IO wrapper). Reset Logic is added to control the PLLs.

 

Verification - Simulation

 

 

FPGA - Hardware Spartan 3

 

FPGA - Hardware Cyclone 3

Reverb von Terrasic Cyclone 4

 

Demos

Download an echo delay example for Digilent Spartan 3E: audiotest.zip

 

Jürgen Schuhmacher - 2010