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Advanced Audio Recording

A real analog synthesizer with a Xilinx PLD

This page shows a new way to create an analog like music synthesizer using a programmable logic device (PLD). Being a digital circuit in the first place, PLDs are usually programmed that way that the logical function is defined and translated into time discrete behavior by operating with clocked circuits using the available structures. This makes the logical function independent from switching and timing characteristics so analog behavior of the device are ignored as much as possible.

 Giving the analog behavior a chance, I created an oscillator based synthesis module which works similar to classical digital organs: Typically there is one high frequency oscillator present, driving the whole sound synthesis unit. Low frequencies are derived from the master oscillator by frequency division. Therefore a self oscillating circuit and some frequency dividers should be the a good idea. But there were some issues.

To understand the problems, a more detailed view on PLDs is necessary:

Self oscillating circuits are not a standard type of element available in PLDs since they are only required for special applications like self starting reset circuits and when there is no external clock. These functions have to be created manually by e.g. putting an odd number of inverters into a chain with feed back coupling. Depending on the chain length, switching characteristics and outer influences like temperature, one will get a more or less stable oscillator with a non dedicated frequency. Short chains of 5-7 inverters to 100MHz - 200MHz in current PLDs.

Once having created such an OSC, the whole circuit which is driven by it, runs on this frequency. From that on it should have been possible to create the desired frequencies for sound synthesis if the frequency is known well enough to set up the dividers. Because of the first unknown frequency which will be PLD dependent, a kind of PLL will have to be instantiated to softly synch to a given dedicated frequency from the outside. The first approach is to apply a digital oscillator of a known frequency to a pin of the PLD and sample it's input to afterwards toggle the oscillators output signal. This commonly used technique works best to synch the data frequency of any clock domain to a foreign domain in order to maintain the same throughput in the long run. But we need something different: The system frequency has to be changed so the inverter chain has to be affected directly.

The idea is to create a switchable chain of two different lengths and find out if the resulting frequency is too low or too high and then adjust it dynamically. Therefore a self oscillating PLL-like circuit is created using a local frequency divider with adjustable parameter is used. The strategy is, that the divider is dynamically controlled that way, that the division result creates approximately the frequency given at the input pin. The phase of the pin is observed and if the inner clock edge comes too late, the self oscillation clock generator is accelerated by using the shorter inverter chain. If the phase delay still rises, the devisor value is decreased and vice versa. This first leads to the fact, that the divider value is adjusted to nearly any incoming clock frequency and once reached this state, only the chain length toggles to keep the inner OSC in phase. To work properly the chain length has to by large enough that the switching does not affect to clock edge wave running though the circuit and divider adjustment has to be at least 10-20 times slower, so it will take some time before the clock is totally synched - possible up to a second or more. But this should not bother us since it happens only once during start up.

PLD  based analog oscillator

The obtained master frequency of 1 MHz is then used to derive the musical frequencies from C2 to C6, but there is again another new issue: The circuit produces the desired analog behavior very well, but frequency movement is totally the same for all music frequencies. So the next idea was to instantiate 12 different oscillators thus create individual sets of waves from the OSCs.

But how can waves be created "the analog way"?

Whenever a counter of the 12 primary dividers or one of the derived frequencies toggles, we have a full square wave already present. Phase offsets and modulation can be easily be applied by adding an initial value to the counters or change them with more then +1/-1  with each clock cycle. The dividers' outputs are routed to 48 external pins, where analog circuits is attached acting as band width filters emphasizing the particular frequency. They outputs are summed up at this point. In a simplified version it was tried to group some of the outputs and use only a reduced number of bandwidth limiters which worked also properly.


PLD - based pseudo PLL sound synthesis with self running oscillators


Running the circuit with independent oscillators was indeed a good idea. There was be always a coincidental and unpredictable phase relation between the voices which makes the sound more natural.



© 2001 - Jürgen Schuhmacher